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Today, solid state image sensors are used in many applications like in mobile phones, video surveillance systems, embedded medical imaging and industrial vision systems. These image sensors require the integration in the focal plane (or near the focal plane) of complex image processing algorithms. Such devices must meet the constraints related to the quality of acquired images, speed and performance of embedded processing, as well
as low power consumption.
To achieve these objectives, low-level analog processing allows extracting the useful information in the scene directly. For example, edge detection step followed by a local maxima extraction will facilitate the high-level processing like objects pattern recognition in a visual scene. Our goal was to design an intelligent image sensor prototype achieving high-speed image acquisition and non-linear image processing (like local minima and maxima calculations). For this purpose, we present in this article the design and test of a 64x64 pixels image sensor built in a standard CMOS Technology 0.35μm including non-linear image processing.
The architecture of our sensor, named nLiRIC (non-Linear Rapid Image Capture), is based on the implementation of an analog Minima/Maxima Unit. This MMU calculates the minimum and maximum values (non-linear functions), in real time, in a 2x2 pixels neighbourhood. Each MMU needs 52 transistors and the pitch of one pixel is 40x40μm.
The total area of the 64x64 pixels is 11mm2. Our tests have shown the validity of the main functions of our new image sensor like fast image acquisition (1K frames per second), minima/maxima calculations in less then one ms.
Date : du 2012-09-13 au 2012-09-30
Lieu : Université de Bourgogne - Dijon France
Thèmes scientifiques :
C - Algorithme-architecture en traitement du signal et des images
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